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| FEATURES s s s LTC1923 High Efficiency Thermoelectric Cooler Controller DESCRIPTIO The LTC(R)1923 is a pulse width modulator intended for thermoelectric cooler (TEC) or heater applications requiring either unidirectional or bidirectional drive circuits. All of the necessary control circuitry and two sets of complementary output drivers are integrated into the LTC1923 to drive a full bridge, providing an efficient means of bidirectional current flow to the TEC. An accurate temperature control loop to stabilize the temperature of a laser diode system is easily achieved with the addition of just a few external components. Typical temperature setpoint accuracy of 0.1C is achievable with the LTC1923. Adding an instrumentation amplifier front end allows setpoint stability of 0.01C. The part features independent adjustable heating and cooling pulse-by-pulse current limit, current soft-start for controlled start-up, output slew rate control to reduce system noise, differential current sense and voltage amplifiers and a host of auxiliary circuits to protect the laser and provide redundant system monitoring. , LTC and LT are registered trademarks of Linear Technology Corporation. s s s s s s s s s High Efficiency, Low Noise Topology Adjustable Output Slew Rate Reduces EMI Full-Bridge Controller for Bidirectional Current Control Adjustable Pulse-by-Pulse Bidirectional TEC Current Limit Open/Shorted Thermistor Indication Solution Footprint in Less Than 0.6" x 0.8" (Double-Sided PCB) Available in 5mm x 5mm QFN and 28-Pin SSOP Packages TEC Voltage Clamping TEC Current, Voltage and Heat/Cool Status Outputs Adjustable/Synchronizable Oscillator Frequency Reduces Filter Component Size and System Noise 2.5V Reference Voltage Output 2.7V Minimum Operating Voltage APPLICATIO S s s s Laser-Based Fiber Optic Links Medical Instruments CPU Temperature Regulators TYPICAL APPLICATIO 10k 0.1% Laser Temperature Control Loop Achieving Setpoint Stability of 0.01C 10k PLLLPF 82k REF 10k NTC TMP CMD LTC1658 VOUT RT CT VREF PDRVB NDRVB VDD LTC1923 1F AGND SS ILIM VSET FAULT VTHRM C1, C2: TAIYO YUDEN JMK325BJ226MM-T (X7R) L1, L2: SUMIDA CDRH6D2B-220NC *MNA, MPA: SILICONIX Si9801 **MNB, MPB: SILICONIX Si9801 H/C VTEC PGND NDRVA PDRVA CS + CS - ITEC TEC + TEC - 4 3 1 RS 2 1F MPA* L1 10H C1 MNB** 22F COOLER TEC L2 10H C2 22F MNA* VREF 330pF 1F + - RSLEW VDD SDSYNC CNTRL EAOUT FB REF LTC2053 A = 10 4.7F 10M 100k U U U VDD 10F MPB** 1923 TA01 1923f 1 LTC1923 ABSOLUTE AXI U RATI GS VDD to GND................................................. - 0.3V to 6V SDSYNC, RSLEW ......................................... - 0.3V to 6V FB, CNTRL, VTHRM, ILIM, VSET ..................... - 0.3V to 6V CS +, CS -, TEC +, TEC - .................................- 0.3V to 6V PACKAGE/ORDER I FOR ATIO SDSYNC PLLLPF RSLEW VREF NC NC RT CT ORDER PART NUMBER LTC1923EUH 24 PDRVB 23 NDRVB 22 VDD 21 VDD 20 PGND 19 NDRVA 18 PDRVA 17 CS + 32 31 30 29 28 27 26 25 CNTRL 1 EAOUT 2 FB 3 AGND 4 NC 5 SS 6 ILIM 7 VSET 8 9 10 11 12 13 14 15 16 FAULT VTEC VTHRM TEC - TEC + ITEC H/C CS - PIN 1 TOP VIEW UH PACKAGE 32-LEAD PLASTIC QFN TJMAX = 125C, JA = 34C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted. SYMBOL PARAMETER Input Supply VDD UVLO UVHYST IDD IDDSHDN SHDNTH Operating Supply Voltage Undervoltage Lockout Hysteresis Operating Supply Current Shutdown IDD Shutdown Threshold Low to High Threshold High to Low No Output Load, Outputs Not Switching SDSYNC = 0V Measured at PDRVA, PDRVB 0.3 q q q CONDITIONS 2 U U W WW U W (Note 1) FAULT, H/C ................................................. - 0.3V to 6V Operating Temperature Range (Note 2) .. - 40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C TOP VIEW PLLLPF RSLEW SDSYNC CNTRL EAOUT FB AGND SS ILIM 1 2 3 4 5 6 7 8 9 28 RT 27 CT 26 VREF 25 PDRVB 24 NDRVB 23 VDD 22 PGND 21 NDRVA 20 PDRVA 19 CS + 18 CS - 17 ITEC 16 TEC + 15 TEC - ORDER PART NUMBER LTC1923EGN VSET 10 FAULT 11 VTHRM 12 H/C 13 VTEC 14 GN PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 120C/W MIN 2.7 TYP MAX 5.5 UNITS V V mV mA A V 2.6 50 130 2 10 0.8 2.7 4 25 1.4 1923f LTC1923 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted. SYMBOL PARAMETER Reference VREF VREFGD LDREG VREFISC fOSCI fOSC OSCPK OSCVLY CTICH CTIDIS IPLLLPF Reference Output Voltage VREF Good Threshold Load Regulation Short-Circuit Current Initial Oscillator Frequency Frequency Variation CT Ramp Peak CT Ramp Valley CT Charge Current CT Discharge Current Phase Detector Output Current Sinking Sourcing Master Threshold On PLLLPF Pin Shutdown Delay to Output Input Offset Voltage Open-Loop Gain Common Mode Input Range FB and CNTRL Input Bias Currents Output High Output Low Sourcing Current Sinking Current Gain-Bandwidth Product Amplifier Gain Amplifier Offset Output Sourcing Load Regulation Output Sinking Load Regulation -3dB Frequency Current Limit Threshold Current Limit Delay to Output Soft-Start Charge Current Soft-Start Current Limit Threshold ILIM Current Limit Threshold SS = 0.75V SS = 0.5V, Measured at CS+, CS- ILIM = 0.5V, Measured at CS+, CS- - 2.5 50 50 Measured at ITEC CS + - CS - = 100mV, I LOAD = 0 to - 50A CONDITIONS No Load q MIN 2.462 2.450 TYP 2.5 2.25 10 5 MAX 2.538 2.550 2.45 25 20 UNITS V V V mV mV mA VREF Rising Threshold ILOAD = -1mA to -10mA VDD = 2.7V to 5.5V VREF = 0V RT = 10k, CT = 330pF VDD = 2.7V to 5V, CT = 330pF, RT = 10k q LINEREG Line Regulation Oscillator and Phase-Locked Loop 10 190 q 20 225 225 1.5 0.5 -150 150 260 270 1.6 0.6 kHz kHz V V A A 165 1.4 0.4 CT = 0.3V, RT = 10k CT = 1.8V, RT = 10k - 1.1 fSYNC < fOSC fSYNC > fOSC Measured at SDSYNC Pin 20 EAOUT = 1V, VCM = 2.5V EAOUT = 0.45V to 1.55V, CNTRL = 2.5V EAOUT = 1V FB = CNTRL = 1.25 ILOAD = - 100A ILOAD = 100A EAOUT = 1V, FB = 2.4V, CNTRL = 2.5V EAOUT = 1V, FB = 5V, CNTRL = 2.5V f = 100kHz (Note 3) 1 0.2 - 100 -18 PLLGAIN Gain from PLLLPF to RT - 0.9 12 -12 - 0.7 V/V A A V s MSTTH SDDLY VOS AOL VCM IIB VOH VOL ISOURCE ISINK GBW ACS CSOFF ITECH ITECL f3dB ILIMTH ILIMDLY SSICHG SSILIM ILIM VDD - 0.7 VDD - 0.4 45 18 80 VDD + 0.2 100 1.65 0.3 -1.5 2 2 10 - 15 -2 0.1 0.1 500 q Error Amplifier mV dB V nA V 0.45 - 0.5 V mA mA MHz V/V 10 0.2 0.2 165 450 - 0.5 90 90 mV V V kHz mV ns A mV mV Current Sense Amplifier CS + - CS - = 100mV, ILOAD = 0 to 50A (Note 3) Measured at CS+, CS- 125 145 300 - 1.5 70 70 1923f 3 LTC1923 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VDD = 5V, RSLEW = VDD, SDSYNC = VDD, RT = 10k, CT = 330pF unless otherwise noted. SYMBOL PARAMETER TEC Voltage Amplifier ATEC TECOFF TECCMR VTECH VTECL f3dB OUTH OUTL tRISE tFALL trSLEW tfSLEW trSLEW tfSLEW SLEWVT DLY Fault OPENTH SHRTTH FLTV DIRH DIRL HCV Open Thermistor Threshold Shorted Thermistor Threshold Fault Output Low Voltage Low-to-High Threshold High-to-Low Threshold H/C Output Low Voltage VSET = 5V, Measured with Respect to VSET VSET = 5V, Measured with Respect to GND 1mA Into FAULT, During Fault TEC - = 2.5V, Measured with Respect to TEC - Sensed When H/C Toggles Low TEC - = 2.5V, Measured with Respect to TEC - Sensed When H/C Toggles High 1mA Into Pin - 410 0.975 150 50 - 50 150 Note 3: Guaranteed by design, not tested in production. 300 300 mV V mV mV mV mV Amplifier Gain Amplifier Offset Common Mode Rejection Output High Voltage Output Low Voltage -3dB Frequency Output High Voltage Output Low Voltage Output Rise Time Output Fall Time Output Rise Time Output Fall Time Output Rise Time Output Slew Fall Time RSLEW Disable Threshold Output Dead Time RT = 10k Measured at VTEC, VCM = 2.5V 0.1V < VCM < 4.9V ILOAD = -50A ILOAD = 50A (Note 3) IOUT = - 100mA IOUT = 100mA CLOAD = 1nF CLOAD = 1nF CLOAD = 1nF, RSLEW = 10k CLOAD = 1nF, RSLEW = 10k CLOAD = 1nF, RSLEW = 100k CLOAD = 1nF, RSLEW = 100k 4 4.7 0.98 1 -7 60 4.9 0.1 1 4.5 0.7 20 20 20 20 90 90 2.75 90 1.2 0.3 1.02 V/V mV dB V V MHz V V ns ns ns ns ns ns V ns CONDITIONS MIN TYP MAX UNITS Output Drivers Direction Comparator Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1923E is guaranteed to meet specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. 1923f 4 LTC1923 TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency vs Temperature 265 OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) 1800 CT = 330pF RT = 10k 245 1000 800 600 400 200 CT = 150pF 205 VREF (V) 225 185 165 -50 -20 10 40 70 TEMPERATURE (C) VREF vs IREF for Different Temperatures 2.515 2.510 2.505 125 TA = 125C 150 DEAD TIME (ns) VREF (V) 2.495 2.490 2.485 2.480 2.475 2.470 0 5 IREF (mA) 1923 G04 100 VDD = 5V 75 RISE TIME (ns) 2.500 TA = 25C TA = -50C 10 Error Amplifier Offset Voltage vs Temperature 1.5 OPEN THERMISTOR THRESHOLD (V) 4.60 SHORTED THERMISTOR THRESHOLD (V) ERROR AMPLIFIER VIO (mV) 1.0 0.5 0 -0.5 -1.0 -50 -20 10 40 70 TEMPERATURE (C) UW 100 100 Oscillator Frequency vs RT 1600 1400 1200 CT = 68pF 2.500 VDD = 2.7V, 5V TA = 25C 2.510 VREF vs Temperature 2.505 2.495 2.490 CT = 330pF 130 0 5 10 RT (k) 15 20 1923 G02 2.485 -50 -20 10 40 70 TEMPERATURE (C) 100 130 1923 G01 1923 G03 Output Dead Time vs RT TA = 25C 250 Output Rise/Fall Time vs RSLEW TA = 25C 200 VDD = 2.7V 150 100 50 50 15 25 5 7.5 10 RT (k) 12.5 15 1923 G05 0 0 100 200 RSLEW (k) 300 1923 G06 Open Thermistor Threshold vs Temperature 1.00 VSET = 5V 4.59 Shorted Thermistor Threshold vs Temperature VSET = 5V 0.99 4.58 0.98 4.57 0.97 4.56 0.96 130 4.55 -50 -20 10 40 70 TEMPERATURE (C) 100 130 0.95 -50 -20 10 40 70 TEMPERATURE (C) 100 130 1923 G07 1923 G08 1923 G09 1923f 5 LTC1923 TYPICAL PERFOR A CE CHARACTERISTICS Current Limit Threshold vs Temperature 165 CURRENT LIMIT THRESHOLD (mV) 160 155 150 145 140 135 130 125 -50 -20 40 70 10 TEMPERATURE (C) 100 130 POWER LOSS (W) 0.5 0.4 VDD = 5V 0.3 VDD = 3.3V 0.2 0.1 0 0 0.5 TEC CURRENT (A) 1 1923 G11 TEC CLAMP VOLTAGE (V) 6 UW 1923 G10 System Power Loss vs TEC Current 0.7 0.6 2.530 TA = 25C 2.550 TEC Clamp Voltage vs Temperature 2.510 2.490 2.470 2.450 -50 -20 40 70 10 TEMPERATURE (C) 100 130 1923 G12 Representative Waveforms for NDRVA, NDRVB, TEC Current and CS + - CS - CH1: TEC CURRENT (500mA/DIV) CH2: VOLTAGE ACROSS 0.1 SENSE RESISTOR (CS + - CS -) 100mV/DIV CH3: NDRVA (5V/DIV) CH4: NDRVB (5V/DIV) VDD = 5V RTEC = 2.5 RS = 0.1 1923 G15.tif Representative Waveforms for TEC Current, CS + - CS - and ITEC CH2: VOLTAGE ACROSS 0.1 SENSE RESISTOR RS (CS + - CS -) 100mV/DIV CH2 CH3: VOLTAGE ON ITEC PIN EQUAL TO TEN TIMES THE ABSOLUTE VALUE OF CH2 (200mV/DIV) CH1: TEC CURRENT (500mA/DIV) CH1, CH3 VDD = 5V RTEC = 2.5 RS = 0.1 1923 G16.tif 1923f LTC1923 TYPICAL PERFOR A CE CHARACTERISTICS Long-Term Cooling Mode Stability Measured in Environment that Steps 20 Degrees Above Ambient Every Hour. Data Shows Resulting 0.008C Peak-to-Peak Variation, Indicating Thermal Gain of 2500. 0.0025C Baseline Tilt Over Plot Length Derives From Varying Ambient Temperature Identical Test Conditions as Above, Except in Heating Mode. TEC's Higher Heating Mode Efficiency Results in Higher Thermal Gain. 0.002C Peak-to-Peak Variation Is 4x Stability Improvement. Baseline Tilt, Just Detectable, Shows Similar 4x Improvement vs Above UW 1923 G13.tif 1923 G14.tif 1923f 7 LTC1923 PI FU CTIO S PLLLPF (Pin 1/Pin 30): This pin serves as the lowpass filter for the phase-locked loop when the part is being synchronized. The average voltage on this pin equally alters both the oscillator charge and discharge currents, thereby changing the frequency of operation. Bringing the voltage on this pin above VDD - 0.4V signifies that the part will be used as the synchronization master. This allows multiple devices on the same board to be operated at the same frequency. The SDSYNC pin will be pulled low during each CT charging cycle to facilitate synchronization. RSLEW (Pin 2/Pin 31): Placing a resistor from this pin to AGND sets the voltage slew rate of the output driver pins. The minimum resistor value is 10k and the maximum value is 300k. Slew rate limiting can be disabled by tying this pin to VDD, allowing the outputs to transition at their maximum rate. SDSYNC (Pin 3/Pin 32): This pin can be used to disable the IC, synchronize the internal oscillator or be the master to synchronize other devices. Grounding this pin will disable all internal circuitry and cause NDRVA and NDRVB to be forced low and PDRVA and PDRVB to be forced to VDD. EAOUT will be forced low. FAULT will also be asserted low indicating a fault condition. The pin can be pulled low for up to 20s without triggering the shutdown circuitry. The part can either be slaved to an external clock or can be used as the master (see Applications Information for a more detailed explanantion). CNTRL (Pin 4/Pin 1): Noninverting Input to the Error Amplifier. EAOUT (Pin 5/Pin 2): Output of the Error Amplifier. The loop compensation network is connected between this pin and FB. The voltage on this pin is the input to the PWM comparator and commands anywhere between 0% and 100% duty cycle to control the temperature of the temperature sense element. FB (Pin 6/Pin 3): The Inverting Input to the Error Amplifier. This input is connected to EAOUT through a compensating feedback network. AGND (Pin 7/Pin 4): Signal Ground. All voltages are measured with respect to AGND. Bypass VDD and VREF with low ESR capacitors to the ground plane near this pin. 8 U U U (GN Package/UH Package) SS (Pin 8/Pin 6): The TEC current can be soft-started by adding a capacitor from this pin to ground. This capacitor will be charged by a 1.5A current source. This pin connects to one of the inverting inputs of the current limit comparator and allows the TEC current to be linearly ramped up from zero. The voltage on this pin must be greater than 1.5V to allow the open/shorted thermistor window comparitor to signal a fault. ILIM (Pin 9/Pin 7): A voltage divider from VREF to this pin sets the current limit threshold for the TEC. If the voltage on this pin is set higher than 1V, then ILIMIT = 150mV/RS as that is the internal current limit comparator level. If the voltage on this pin is set less than 1V, the current limit value where the comparator trips is: ILIMIT = [0.15 * RILIM1 * VREF]/[(RILIM1 + RILIM2) * RS] VSET (Pin 10/Pin 8): This is the input for the setpoint reference of the temperature sense element divider network or bridge. This pin must be connected to the bias source for the thermistor divider network. FAULT (Pin 11/Pin 9): Open-drain output that indicates by pulling low when the voltage on VTHRM is outside the specified window, the part is in shutdown, undervoltage lockout (UVLO), or the reference is not good. When the voltage on VTHRM is outside the specified window, it signifies that the thermistor impedance is out of its acceptable range. This signal can be used to flag a microcontroller to shut the system down or used to disconnect power from the bridge. See Applications Information for using this signal for redundant protection. VTHRM (Pin 12/Pin 10): Voltage Across the Thermistor. If the voltage on this pin is outside the range between 410mV below VSET and 0.2 * VSET, the FAULT pin will be asserted (and latched) low indicating that the thermistor temperature has moved outside the acceptable range. H/C (Pin 13/Pin 11): This open-drain output provides the direction information of the TEC current flow. If TEC + is greater than TEC -, which typically corresponds to the system cooling, this output will be a logic low. If the opposite is the case, this pin will pull to a logic high. 1923f LTC1923 PI FU CTIO S VTEC (Pin 14/Pin 12): Output of the differential TEC voltage amplifier equal to the magnitude of the voltage across the TEC. TEC- (Pin 15/Pin 13): Inverting Input to the Differential TEC Voltage Amplifier. This amplifier has a fixed gain of 1 with its output being the voltage across the TEC with respect to AGND. This input, along with TEC+, signifies whether the TEC is heating or cooling the laser as indicated by the H/C pin. TEC + (Pin 16/Pin 14): Noninverting Input to the Differential TEC Voltage Amplifier. ITEC (Pin 17/Pin 15): Output of the Differential Current Sense Amplifier. The voltage on this pin is equal to 10 * (ITEC + IRIPPLE) * RS, where ITEC is the thermoelectric cooler current, IRIPPLE is the inductor ripple current and RS is the sense resistor used to sense this current. This voltage represents only the magnitude of the current and provides no direction information. Current limit occurs when the voltage on this pin exceeds the lesser of 1.5 times the voltage on SS, 1.5 times the voltage on ILIM or 1.5V. When this condition is present, the pair of outputs, which are presently conducting, are immediately turned off. The current limit condition is cleared when the CT pin reaches the next corresponding peak or valley (see Current Limit section). CS - (Pin 18/Pin 16): Inverting Input to the Differential Current Sense Amplifier. CS + (Pin 19/Pin 17): Noninverting Input of the Differential Current Sense Amplifier. The amplifier has a fixed gain of 10. PDRVA, PDRVB (Pins 20, 25/Pins 18, 24): These pushpull outputs are configured to drive the opposite high side PMOS switches in a full-bridge arrangement. U U U (GN Package/UH Package) NDRVA, NDRVB (Pins 21, 24/Pins 19, 23): These pushpull outputs are configured to drive the opposite low side switches in a full-bridge arrangement. PGND (Pin 22/Pin 20): This is the high current ground for the IC. The external current sense resistor should be referenced to this point. VDD (Pin 23/Pins 21, 22): Positive Supply Rail for the IC. Bypass this pin to PGND and AGND with > 10F low ESL, ESR ceramic capacitors. The turn on voltage level for VDD is 2.6V with 130mV of hysteresis. VREF (Pin 26/Pin 27): This is the output of the Reference. This pin should be bypassed to GND with a 1F ceramic capacitor. The reference is able to supply a minimum of 10mA of current and is internally short-circuit current limited. CT (Pin 27/Pin 28): The triangular wave oscillator timing capacitor pin is used in conjunction with RT to set the oscillator frequency. The equation for calculating frequency is: fOSC = 0.75 Hz R T * CT RT (Pin 28/Pin 29): A single resistor from RT to AGND sets the charging and discharging currents for the triangle oscillator. This pin also sets the dead time between turning one set of outputs off and turning the other set on to ensure the outputs do not cross conduct. The voltage on this pin is regulated to 0.5V. For best performance, the current sourced from the RT pin should be limited to a maximum 150A. Selecting RT to be 10k is recommended and provides 90ns of dead time. 1923f 9 RSLEW LTC1923 DIGITAL PHASE DETECTOR + PDRVB NDRVA 90ns DELAY VDD - 0.4V MASTER COMPARATOR DELAY IRT 0.7V + - PDRVB SDSYNC 1 = SHDN 20s DELAY - gm 0.3V FU CTIO AL DIAGRA gm NDRVB RT OSCILLATOR - - + Q S RAMP = 0.5V - 1.5V TEC CLAMP Q S Q Q R ENABLE OSC PEAK 1V RQ QB VDD PGND 1.5A SS QB SQ Q R CT FB - + 2.5V Q R ENABLE OSC VALLEY gm CNTRL ERROR AMPLIFIER + EAOUT - - - + OPEN/SHORTED THERMISTOR CURRENT LIMIT - VTEC VSET 350mV ILIM 2R S Q R R TSD ENABLE 1.5V X10 CS AMP CS + + INPUT SELECT CS - VTHRM - 0.2VSET VDD VBG 1 = REFGOOD UVLO 2.5V LDO REF VREF GOOD COMPARATOR 1 = UVLO ENABLE REFGOOD UVLO SHDN TSD AGND VREF - ENABLE SS + X1 TEC AMP INPUT SELECT - TEC + + TEC - DIRECTIONAL COMPARATOR FAULT ITEC VTEC H/C - 1923 BD W + 0.5V + + IRT - SHUTDOWN COMPARATOR NDRVA PDRVA NDRVA 90ns DELAY U + + - - 10 1 4 VDD + VBE ISLEW 1/2 VDD VDD - 1 = NO SLEW LIMITING SWITCHES OPEN + SLEW LIMITING PDRVA PLLLPF U VDD 1923f LTC1923 OPERATIO MAIN CONTROL LOOP The LTC1923 uses a constant frequency, voltage mode architecture to control temperature. The relative duty cycles of two pairs of N-/P-channel external MOSFETs, set up in a full-bridge (also referred to as an H-bridge) configuration are adjusted to control the system temperature. The full-bridge architecture facilitates bidirectional current flow through a thermoelectric cooler (TEC) or other heating element. The direction of the current flow determines whether the system is being heated or cooled. Typically a thermistor, platinum RTD or other appropriate element is used to sense the system temperature. The control loop is closed around this sense element and TEC. The voltage on the output of the error amplifier, EAOUT, relative to the triangle wave on CT, controls whether the TEC will be heating or cooling. A schematic of the external full bridge is shown in Figure 1. The "A" side of the bridge is comprised of the top left PMOS, MPA, and lower right NMOS, MNA. The gates of these devices are attached to the PDRVA and NDRVA outputs of the LTC1923, respectively. The "B" side of the bridge is comprised of PMOS, MPB and NMOS, MNB. The gates of these MOSFETs are controlled by the PDRVB and NDRVB outputs of the LTC1923. The "A" side of the bridge is turned on (NDRVA is high and PDRVA is low) when the output of the error amplifier is less than the voltage on the CT pin as shown in Figure 2. VDD PDRVB PDRVA MPA VTECOOLER TEC MPB NDRVB NDRVA CS + CS - TEC + TEC - Figure 1. Full-Bridge Schematic U For this condition, the state of each output driver is as follows: PDRVA is low, NDRVA is high, PDRVB is high and NDRVB is low. When the voltage on EAOUT is greater than the voltage on the CT pin, the "B" side of the bridge is turned on. The average voltage across the TEC, VTECOOLER, is approximately: VTECOOLER = VTEC+ - VTEC- = VDD * (DA - DB) where VDD = the full-bridge supply voltage VTECOOLER = VTEC+ - VTEC- DA = the duty cycle of the "A" side of the bridge or the amount of time the "A" side is on divided by the oscillator period DB = the duty cycle of the "B" side of the bridge Duty cycle terms DA and DB are related by the following equation: DA = 1 - DB In steady-state, the polarity of VTECOOLER indicates whether the system is being heated or cooled. Typically, when current flows into the TEC + side of the cooler, the system is being cooled and heated when current flows out of this terminal. Note: Do not confuse the TEC+ side of the TEC with the TEC+ input of the LTC1923, although these two points should be connected together. EAOUT CT NDRVA MNB MNA + - A SIDE ON B SIDE ON PDRVA 3 RS 4 2 1923 F01 1 NDRVB PDRVB 1923 F02 Figure 2. Error Amplifier Output, CT and Output Driver Waveforms 1923f 11 LTC1923 OPERATIO PROTECTION FEATURES Many protection features have been integrated into the LTC1923 to ensure that the TEC is not overstressed or the system does not thermally run away. These features include pulse-by-pulse current limiting, TEC voltage clamping and open/shorted thermistor detection. Current Limit The peak current in the full bridge during each switching cycle can be limited by placing a sense resistor, RS, from the common NMOS source connections of MNA and MNB to ground. The CS + and CS - connections should be made as shown in Figure 1. Current limit is comprised of a fixed gain of ten differential amplifier, an attenuator (resistor divider) and a current limit comparator. A detailed diagram of the circuitry is shown in Figure 3. The differential amplifier output, ITEC, is provided to allow the user the ability to monitor the instantaneous current flowing in the bridge. If an average current is desired, an external RC filter can be used to filter the ITEC output. Approximately 50ns of leading edge blanking is also internally integrated to prevent nuisance tripping of the current sense circuitry. It relieves the filtering requirements for the CS input pins. During a switching cycle, current limit occurs when the voltage on ITEC exceeds the lowest of the following three conditions: 1) 1.5 times the voltage on the SS pin, 2) 1.5 times the voltage on the ILIM pin or 3) 1.5V. When a current limit condition is sensed, all four external FETs are immediately shut off. These devices are turned back on only after CT reaches the same state (either charging or TEC + NDRVA TEC - NDRVB CS+ CS - ITEC 2R ILIM SS 12 U discharging) as when the current limit condition occurred. For instance, if CT is charging when current limit occurs, the outputs are forced off for the remainder of this charging time, the entire CT discharge time, and are only re-enabled when CT reaches its valley voltage and begins charging again. An analogous sequence of events occurs if current limit is tripped while CT is being discharged. The full-bridge current can be soft-started (gradually increased) by placing a capacitor from the SS pin to ground. A 1.5A current is sourced from the chip and will charge the capacitor. This limits the inrush current at startup and allows the current delivered to the TEC to be linearly increased from zero. The LTC1923 features a dedicated pin, ILIM, to adjust current limit. If the voltage placed on ILIM is greater than 1V, the default current limit, ILIMIT, is: ILIMIT = 150mV/RS where RS = the current sense resistor. Utilizing the ILIM pin allows the current limit threshold to be easily set and adjusted (the current limit threshold can also be adjusted by changing RS). More importantly, it facilitates independent setting of the heating and cooling current limits with the addition of one transistor. Figure 4 shows how to implement this using three resistors and an external NMOS, M1. In many applications, a higher cooling capability is desired. When TEC + is greater than TEC -, the H/C output is in a low state signifying that the system is being cooled (this is typical for most lasers). + INPUT SELECT CURRENT SENSE AMPLIFIER A = 10 NDRVA NDRVB R LEB 1V PULSE-BY-PULSE CURRENT LIMIT S Q SHUT OUTPUTS OFF 1923 F03 - + - - - OSCILLATOR PEAK/VALLEY 1.5A R Figure 3. Current Sense Circuitry 1923f LTC1923 OPERATIO VREF RILIM2 RILIM1 M1 2N7002 RLIM3 H/C Figure 4. Independently Heating/Cooling Current Limit Transistor M1 is off and the current limit threshold is given by: ILIMIT = 0.15 * RILIM1 * VREF (RILIM1 + RILIM2 ) * RS When TEC - is greater than TEC +, the open-drain output, H/C, pulls high through RPULLUP, causing M1 to turn on. The current limit value is given by: ILIMIT = (RILIM2 + RILIM1 RILIM3 ) * RS 0.15 * RILIM1 RILIM3 * VREF reducing the current limit threshold for heating. If the heating current limit needs to be greater than the cooling limit, an extra inversion can be added. FAULT Open/Shorted Thermistor Detection The temperature sense element (NTC thermistor, platinum RTD or other appropriate component) must be properly connected in order for the system to regulate temperature. If the sense element is incorrectly connected, the system will be unable to control the temperature and the potential exists for the system to thermally run away. A TEC by nature produces a temperature differential between opposite sides of the device depending upon how much current is flowing through it. There is a maximum limit to the amount of temperature differential that can be produced, which depends upon a number of physical PDRVB PDRVA TEC NDRVB NDRVA CS + 3 1923 F05 U VDD RPULLUP ILIM LTC1923 + - TEC+ TEC - parameters including the size of the TEC and how well heatsinked the device is. The TEC itself dissipates power to produce the temperature differential, generating heat, which must also be removed. At a certain level of power dissipation in the TEC, both sides will begin to heat. This is because the TEC will not be able to pump the selfgenerated heat to the outside world, which can lead to thermal runaway. If the device thermally runs away, damage to the TEC and possibly the components whose temperature is being regulated will occur. The LTC1923 contains two dedicated comparators that directly monitor the voltage on the thermistor. If this voltage is outside the valid window, a latch is set and the FAULT pin is asserted low. The output drivers are not shut off and the control circuitry is not disabled, meaning the part will continue to try to regulate temperature. It is up to the user to use the FAULT signal to disable the appropriate circuitry. There are a couple of ways to do this. The first way is to have the FAULT signal a system microprocessor to shut the system down through the SDSYNC pin. Figure 5 shows another means of protecting the system. External NMOS M1 and PMOS M2 have been added along with two pull-up resistors (RP1 and RP2). M1 and RP2 invert the FAULT signal while M2 acts as a switch in series with bridge. When no fault is present, the gate of M1 is VDD RP1 VDD RP2 M2 M1 VDD 1923 F04 ( ) 1 RS CS - 4 2 Figure 5. Redundant Fault Protection 1923f 13 LTC1923 OPERATIO pulled to VDD forcing the gate of M2 low, which allows the bridge to operate as described earlier. When a fault occurs and FAULT is asserted low, M1 is shut off, forcing the gate of M2 high, shutting that device off. The power path is thus opened, ensuring no current is delivered to the TEC. M2 wants to have low RDS(ON) (less than the value of RS to minimize the power losses associated with it). RP1 and RP2 can be selected on the order of 100k. The lower comparator threshold level is 20% (twenty percent) of VSET and the upper comparator threshold level is 350mV below VSET, where VSET is the voltage applied on the VSET pin. VSET is typically tied to the bias source for the thermistor divider so that any variations will track out. The VSET pin has a high input impedance so that a divideddown voltage can be supplied to this pin to modify the acceptable thermistor impedance range. This is shown in Figure 6. The voltage applied to the VSET pin must be a minimum of 2V. The lower thermistor impedance threshold is: RTH(LOWER) = 0.2 * R1 * R3 R2 + 0.8 * R3 The upper impedance threshold is: RTH(UPPER) = R1(R3 - (R2 + R3)) R2 + (R2 + R3) where = 0.35/VSET. Changing R1 also changes the valid thermistor impedance range. VREF R2 VSET R1 R3 Figure 6. Modifying the Acceptable Thermistor Range 14 U Example: VREF = VSET = 2.5V R1 = 10k, R2 = 0, R3 = open RTH = 10k NTC thermistor with a temperature coefficient of - 4.4%/C at 25C. The acceptable thermistor impedance range before causing a fault is 2.5k to 61k. This corresponds to a valid temperature range of between about -10C and 60C. To ensure the part does not power up with a latched fault at start-up, a fault will not be latched until soft-start has completed. This corresponds to the voltage on SS reaching 1.5V. For a 1F soft-start capacitor, this delay is approximately 1 second. This provides enough time for all supplies (VDD, setpoint reference and VREF) to settle at their final values. TEC Voltage Clamping An internal clamp circuit is included to protect the TEC from an overvoltage condition. When the differential voltage across the TEC exceeds 2.5V, the error amplifier output voltage at the input of the PWM comparator is limited. This clamps the duty cycle of the output drivers, and therefore, the voltage across the TEC. The voltage where clamping occurs can be increased by placing a resistor divider in parallel with the TEC and by making the appropriate connections to TEC + and TEC - as shown in Figure 7. The divider increases the voltage across the TEC, VTECOOLER, where the clamp activates, to: RTE1 RTE1 RTE1 + 1+ * 2.5 - VCM 200k RTE2 100k VTECOOLER = R 1 + TE1 200k + VTHRM RTH 10k NTC 1923 F06 VTECOOLER TEC - VCM TEC + TEC - RTE2 RTE1 1923 F07 Figure 7. Increasing Voltage Clamp Threshold 1923f LTC1923 OPERATIO The terms containing the fixed resistance values are the loading errors introduced by the input impedance of the differential amplifier. A common mode voltage error is also introduced since the addition of RTE1 and RTE2 change the fully differential nature of the amplifier. In order to minimize these errors select RTE1 and RTE2 to be 10k or less. The above equation reduces to: R VTECOOLER 1 + TE1 2.5 RTE2 The Higher Voltage Applications section shows a fully differential means to increase the clamp voltage. This will similarly alter the heating and cooling direction thresholds by the same factor, increasing the thresholds to (RTE1 and RTE2 are assumed to be 10k): R DIRH = 50mV 1 + TE1 RTE2 R DIRL = - 50mV 1 + TE1 RTE2 The output voltage on the VTEC pin, VVTEC, will be reduced by the same ratio: VVTEC = VTECOOLER R 1 + TE1 RTE2 Oscillator Frequency The oscillator determines the switching frequency and the fundamental positioning of all harmonics. The switching frequency also affects the size of the inductor that needs to be selected for a given inductor ripple current (as opposed to TEC ripple current which is a function of both the filter inductor and capacitor). A higher switching frequency allows a smaller valued inductor for a given ripple current. The oscillator is a triangle wave design. A current defined by external resistor RT is used to charge and discharge the capacitor CT. The charge and discharge rates are equal. The selection of high quality external components (5% or better multilayer NPO or X7R ceramic U capacitor) is important to ensure oscillator frequency stability. The frequency of oscillation is determined by: fOSC(kHz) = 750 * 106/[RT(k) * CT(pF)] The LTC1923 can run at frequencies up to 1MHz. The value selected for RT will also affect the delay time between one side of the full bridge turning off and the opposite side turning on. This time is also known as the "break-beforemake" time. The typical value of 10k will produce a 90ns "break-before-make" time. For higher frequency applications, a smaller value of RT may be required to reduce this delay time. For applications where significant slew rate limiting or external gate driver chips are used, a higher value for RT may necessary, increasing the dead time. The "break-before-make" time can be approximately calculated by: tDELAY = RT (k) * 5.75 * 10-9 + 35ns Phase-Locked Loop The LTC1923 has an internal voltage-controlled oscillator (VCO) and phase detector comprising a phase-locked loop. This allows the oscillator to be synchronized with another oscillator by slaving it to a master through the SDSYNC pin. The part can also be designated as the master by pulling the PLLLPF pin high to VDD. This will result in the part toggling the SDSYNC pin at its set oscillator frequency. This signal can then be used to synchronize additional oscillators. When being slaved to another oscillator, the frequency should be set 20% to 30% lower than the target frequency. The frequency lock range is approximately 50%. The phase detector is an edge sensitive digital type, which provides zero degrees phase shift between the external and internal oscillators. This detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The VCO hold-in range is equal to the capture range dfH = dfC = 0.5fO. The output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the PLLLPF pin. A simplified block diagram is shown in Figure 8. 1923f 15 LTC1923 OPERATIO If the external frequency (fPLLIN) is greater than the oscillator frequency, current is sourced continuously out of the PLLLPF pin. When the external frequency is less than the oscillator frequency, current is sunk by the PLLLPF pin. The loop filter components RLP, CLP and CLP2, smooth out current pulses from the phase detector and provide a stable input to the VCO. These components also determine how fast the loop acquires lock. In most instances CLP2 can be omitted, RLP can be set to 1k and CLP can be selected to be 0.01F to 0.1F to stabilize the loop. Make sure that the low side of filter components is tied to AGND to keep unwanted switching noise from altering the performance of the PLL. Figure 9 illustrates three different ways to set the oscillator frequency. In Figure 9a, the oscillator is free running with the frequency determined by RT and CT. In Figure 9b, VDD VDD NC VDD Figure 9. Oscillator Frequency Setup: a) Free Running b) Slaved Operation c) Master/Slave Operation 1923f 16 U the oscillator is slaved to an external clock. Figure 9c illustrates how one LTC1923 can be used as a master to synchronize other LTC1923s or additional devices requiring synchronization. To implement this, determine the values of RT and CT to obtain the desired free-running oscillator frequency of the master by using the equation given in the oscillator frequency section. Tie the master's PLLLPF pin to VDD and the SDSYNC pin to VDD through a resistor RPLL as shown in Figure 9c. RPLL typically can be set to 10k, but may need to be a lower value if higher frequency operation is desired (above 250kHz). Set the slave free-running frequencies to be 20% to 30% less than this. The SDSYNC pin of the master will switch at its free-running frequency (with approximately 50% duty cycle), and this can be used to synchronize the other devices. RPLL EXTERNAL FREQUENCY DIGITAL PHASE FREQUENCY DETECTOR PLLLPF OSC RLP CLP CLP2 CT RT SDSYNCB 1923 F08 Figure 8. Phase-Locked Loop Block Diagram PLLLPF RT RT LTC1923 CLP2 RLP CLP LTC1923 PLLLPF RT RT SDSYNC CT 1923 F09a CLKIN CT SDSYNC CT 1923 F09b CT (9a) Free Running VDD MASTER PLLLPF RT RT RPLL LTC1923 CLP2 (9b) Slave Operation with External Clock-- Set Oscillator Frequency at 70% to 80% of External Clock SLAVE PLLLPF RLP CLP LTC1923 RT 1.2 * RT SDSYNC CT CT SDSYNC CT 1923 F09c CT (9c) Master/Slave Operation--Set Oscillator Frequency of Slave at 70% to 80% of Master LTC1923 APPLICATIO S I FOR ATIO The thermistor may be isolated from the control circuitry. It has a relatively high input impedance and is therefore susceptible to noise pick up. Extreme care should be taken to ensure this signal is noise free by shielding the line (coaxially). A lowpass filter can be added between the thermistor and the input to the LTC2053, but since it is in the signal path, there are limitations on how much filtering can be added. Inductor Ripple Current The current that flows in the bridge can be separated into two components, the DC current that flows through the TEC and the inductor ripple current that is present due to the switchmode nature of the controller. Although the TEC current has its own ripple component, proper filtering will minimize this ripple relative to the inductor ripple current, validating this assumption that the TEC current is constant (see TEC Ripple Current section). A simplified half-circuit of the bridge in steady-state is shown in Figure 10. The current, IL, through the inductor (L) consists of the ripple current (I1) and static TEC current (ITEC). The ripple current magnitude, I1, can be calculated using the following equation: I1 = (VBRIDGE 2 - VTEC 2)/(4 * fOSC where VBRIDGE is the full-bridge supply voltage (typically VDD) fOSC is the oscillator frequency L is the filter inductor value VTEC is the DC voltage drop across the TEC * L * VBRIDGE) PDRVA NDRVB Figure 10. Full-Bridge Half Circuit 1923f U The peak inductor current is equal to ITEC + I1/2 and is the current level that trips the current limit comparator. Keeping the ripple current component small relative to ITEC keeps the current limit trip level equal to the current flowing through the TEC. Example: VBRIDGE = 5V, RTEC = 2.5, VTEC = 2.5V, ITEC = 1A, L = 22H, fOSC = 250kHz. The peak-to-peak ripple current using the above equation is: I1 = 170mA The peak inductor current is therefore 1.085A in order to get 1A of DC TEC current. TEC Ripple Current Every TEC has a fundamental limitation (based mainly on the TEC's physical characteristics) on the maximum temperature differential that it can create between sides. The ability to create this maximum temperature differential is affected by the amount of ripple current that flows through the device, relative to the DC component. An approximation of this degradation due to TEC ripple current is given by the following equation: dT/dTMAX = 1/(1 + N2) where: dT is the adjusted achievable temperature differential dTMAX is the maximum possible temperature differential when the TEC is fed strictly by DC current and is typically specified by the manufacturer N is the ratio of TEC ripple current to DC current TEC manufacturers typically state that N should be no greater than 10%. VBRIDGE MPA IL L ITEC MNB ESR C 1/2 VBRIDGE 1923 F10 W UU + TEC VTEC/2 17 LTC1923 APPLICATIO S I FOR ATIO In this application, the bridge supply voltage, oscillator frequency and external filter components determine the amount of ripple current that flows through the TEC. Higher valued filter components reduce the amount of ripple current through the TEC at the expense of increased board area. Filter capacitor ESR along with inductor ripple current will determine the peak-to-peak voltage ripple across the TEC and therefore the ripple current since the TEC appears resistive. The ripple current through the TEC, ITEC(RIPPLE), is approximately equal to: ITEC(RIPPLE) VBRIDGE2 - VTEC2 16 * fOSC2 * L * C * RTEC * VBRIDGE + (V 2 BRIDGE - VTEC2 * ESR ) 2 * fOSC * L * VBRIDGE * RTEC where: fOSC = the oscillator frequency L = the filter inductor value C = the filter capacitor value RTEC = the resistance of the TEC VTEC = the DC voltage drop across the TEC ESR = the equivalent series resistance of the filter capacitor VBRIDGE = the full-bridge supply voltage typically equal to VDD The equation above shows that there are two components, which comprise TEC ripple current. The first term is the increase in voltage from the charging of the filter capacitor. The second term is due to the filter capacitor ESR and is typically the dominant contributor. Therefore the filter capacitor selected wants to have a low ESR. This capacitor can be made of multilevel ceramic, OS-CON electrolytic or other suitable capacitor. Increasing the oscillator frequency will also reduce the TEC ripple current since both terms have an inverse relationship to operating frequency. Example: VBRIDGE = 5V, RTEC = 2.5, VTEC = 2.5V, L = 22H, C = 22F, fOSC = 250kHz, ESR = 100m ITEC(RIPPLE) = 3.1mA + 13.6mA = 16.7mA 18 U For this example the DC current flowing through the TEC is 1A, making the ripple current equal to approximately 1.7% (this illustrates why ITEC can be approximated to be DC). Closing the Feedback Loop Closing the feedback loop around the TEC and thermistor (or other temperature sensitive element) involves identifying where the thermal system's poles are located and placing electrical pole(s) (and zeroes) to stabilize the control loop. High DC loop gain is desirable to keep extremely tight control on the system temperature. Unfortunately the higher the desired loop gain, the larger the compensation values required to stabilize the system. Given the inherently slow time constants associated with thermal systems (on the order of many seconds), this can lead to unreasonably large component values. Therefore, the amount of loop gain necessary to maintain the desired temperature accuracy should be calculated, and after adding some margin, this should be the target DC loop gain for the system. A block diagram of the system is shown in Figure 11. The gain blocks are as follows: KIA = instrumentation amplifier gain (V/V) KEA = error amplifier gain (V/V) KMOD = modulator gain (d/V) KPWR = power stage gain (V/d) KTEC = TEC gain (C/V) KTHRM = Thermistor Gain (V/C) KIA and KEA are the electrical gains associated with the instrumentation and LTC1923 error amplifier. Switching regulators are sampled systems that convert voltage to duty cycle (d), which explains why the KMOD and KPWR gain terms are expressed as a function of duty cycle and voltage. The TEC converts voltage to temperature change, while the thermistor's impedance and therefore voltage across it changes with temperature. The loop gain can be expressed by the following equation: T (loop gain) = KIA * KEA * KMOD * KPWR * KTEC * KTHRM And the error introduced by the finite gain of the system, VE, can be expressed by: VE = VIN/(1 + T) 1923f W UU LTC1923 APPLICATIO S I FOR ATIO Example: RTHRM = 10k NTC with 4.4%/C at 25C R1 = 10k VREF = 2.5V T = 25C This voltage error translates back into a temperature setpoint error. For this thermistor with a 25C temperature setpoint, the change in thermistor voltage with temperature is given by - 25mV/C. In order to maintain a 0.01C temperature accuracy, this translates into a 250V error signal, VE. The minimum loop gain can now be calculated from the above equation: VE = VIN/(1 + T) A 25C setpoint temperature requires VIN = 1.25V for VREF = 2.5V. The required loop gain is 5000 or 74dB. There are two handles to adjust the loop gain, KIA and KEA, while the other handles are fixed and depend upon the TEC and thermistor characteristics (KTEC and KTHRM), VSET and R1 (KTHRM) and VDD (KMOD and KPWR). The modulator and power gain product is given by: KTHRM VREF R1 10k KIA LTC2053 LTC1923 CT + 10k NTC VE VIN + + - RA ERROR AMP - - Figure 11. Simplified Loop Block Diagram 1923f U KMOD * KPWR = 2 * VDD/VCT = 2 * VDD where VCT = the CT voltage which has a fixed 1V amplitude. The TEC gain depends upon the TEC selected and corresponds to the relationship between the voltage across the device and what temperature differential is created. This gain term changes with operating temperature, and whether the TEC is heating or cooling. TECs are inherently more efficient at heating (and therefore have a higher gain) as compared to cooling. A worst-case rough estimation of the gain can be obtained by taking the maximum TEC voltage required to force a given change in temperature from the TEC specifications: KTEC = dT/VTEC(MAX) The thermistor gain should be linearized around temperature setpoint. Example: Setpoint T = 25C VDD = 5V RTHRM = 10k NTC with 4.4%/C at 25C R1 = 10k VREF = 2.5V dT/VTEC(MAX) = 45C/1.5V = 30C/V KEA KMOD KPWR KTEC VTECOOLER W UU + + POWER STAGE TEC - 1923 F11 RF CF 19 LTC1923 APPLICATIO S I FOR ATIO The linearized thermistor gain around 25C is - 25mV/C. For a minimum loop gain of 5000 as calculated above, the combined gain of the instrumentation and error amplifiers can be calculated: KIA * KEA = T/(KMOD * KPWR * KTEC * KTHRM) KIA * KEA = 5000/(10 * 30 * 0.025) = 667 A combined gain of 1000 can be selected to provide adequate margin. The instrumentation amplifier gain should be set at typically 10, as this attenuates any errors by its gain factor. The error amplifier gain would then be limited to the remainder through the gain setting resistors, RF and RA shown in Figure 11. RF/RA = KEA - 1 The multiple poles associated with the TEC/thermistor system makes it difficult to compensate. Compounding this problem is that there will be significant variations in thermal time constants for the same system, making elaborate compensation schemes difficult to reliably implement. The most robust method (i.e., least prone to oscillation) is to place a dominant pole well below the thermal system time constant () (anywhere from many seconds to minutes). This time constant will set the capacitor value by the following equation: CF = /RF Please refer to Application Note 89 for more detailed information on compensating the loop. Ceramic capacitors are not recommended for use as the integrating capacitor or anywhere in the signal path as they exhibit a piezoelectric effect which can introduce noise into the 10k TMP CMD REF VOUT LTC1658 10k NTC Figure 12. Alternative Compensation Method to Improve Transient Response 1923f 20 U system. The component values shown on the front page of this data sheet provide a good starting point, but some adjustment may be required to optimize the response. Dominant pole compensation does have its limitations. It provides good loop response over a wide range of laser module types. It does not provide the fastest transient response to step changes in temperature. If this is a necessity, a more complex compensation approach as shown in Figure 12 may be required. This approach adds an additional zero into the feedback loop to speed up the transient response. First note that the LTC2053 inputs have been swapped as the LTC1923 error amplifier is now running in an inverting configuration. Capacitor CA is needed to provide the lead term. Resistor RC is used to buffer the LTC2053 from capacitive loading and limit the error amplifier high frequency gain. Since the system thermal pole locations are not known, a qualitative compensation approach must be employed. This entails looking at the transient response when the TEC is heating (due to the inherent higher gain) for a smallsignal step change in temperature and modifying compensation components to improve the response. A reasonable starting point is to select components that mimic the response that will be obtained from the front page of this data sheet. Therefore RA, RB and CB would be selected to be 1M, 1M and 0.47F, respectively. RC should be selected to be a factor of 100 smaller than RA, or on the order of 10k. Make sure that the loop is stable prior to the introduction of capacitor CA. The addition of CA will provide some phase boost in the loop (in effect, offsetting one of the poles associated with the thermal system). Start CC CA RB CB W UU + - REF RC RA 6 FB A = 10 4 CNTRL LTC2053 - LTC1923 5 EAOUT ERROR AMPLIFIER 1923 F12 + LTC1923 APPLICATIO S I FOR ATIO with CA on the order of CB and note its affect on system response. Adjust the values based on observing whether the transient response was improved or not with the goal of reducing CB to improve settling time. As the system thermal poles can vary between "identical" laser modules (i.e., same manufacturer and model), care must be taken to ensure that the values selected provide the desired response even with these thermal term variations. Compensation should also be tailored for each unique laser module as thermal terms can vary significantly between different brands. CC rolls off high frequency gain , minimizing noise in the outputs. It is typically about 25 times smaller than CB. CA, CB and CC should be film capacitors. Temperature Stability It is important to differentiate between temperature accuracy and stability. Since each laser's output maximizes at some temperature, temperature setpoint is typically incremented until this peak is achieved. After this, only temperature stability is required. The predominant parameters which affect temperature stability are the thermistor, the thermistor biasing resistor and any offset drift of the front-end electrical circuitry. Sufficient loop gain ensures that any downstream variations do not contribute signifi- 10k CNTRL 4 TMP CMD REF VOUT LTC1658 10M 4.7F EAOUT 5 1923 F13 10k NTC Figure 13. Simplifed Temperature Control Loop Omitting the LTC2053 Instrumentation Amplifier Front End U cantly to temperature stability. The relatively mild operating conditions inside the laser module promote good longterm thermistor stability. A high quality, low temperature coefficient resistor should be selected to bias the thermistor. If the 10k resistor has a 100ppm/C temperature coefficient, this translates into a 0.18C setpoint temperature differential over a 0C to 70C ambient for a desired 25C laser setpoint. Depending upon the temperature stability requirements of the system, this is very significant. A lower temperature coefficient resistor may therefore be desired. The LTC2053 has maximum offset drift to 50nV/C which translates into less than 0.001C change for a 0C to 70C ambient. The offset drift of the LTC1923 error amplifier divided by the gain of the LTC2053 also affects temperature stability. The offset drift of the LTC1923 (see characteristic curves) is typically 1mV over a 0C to 70C ambient. After attenuation by the LTC2053 gain, this translates into a temperature setpoint variation of 0.004C. Neither of these offsets drifts significantly with aging. Depending upon the setpoint temperature stability requirements of the system, the LTC2053 instrumentation amplifier may not be necessary. Figure 13 shows a simplified schematic with the LTC2053 omitted. + LTC1923 100k FB 6 W UU - ERROR AMPLIFIER 1923f 21 LTC1923 APPLICATIO S I FOR ATIO Noise and Slew Rate Control One disadvantage of switching regulators is that the switching creates wideband harmonic energy. The high frequency content can pose problems to associated circuitry. To combat this issue, the LTC1923 offers a pin called RSLEW that controls the slew rate of the output drive waveforms. Slowing down the transition interval reduces the harmonic frequency content by spreading out the energy over a longer time period. The additional transition time causes some efficiency loss (on the order of 2% to 3%) but significantly improves the high frequency noise reflected onto the input supply. Slew rate control is engaged by placing a resistor from RSLEW to AGND. If slew rate control is not desired, the RSLEW pin should be tied to VDD allowing the output drivers to transition at their fastest rate. The resistor value should be set between 10k (fastest transition) and 300k (slowest transition). This provides about a 10:1 slew rate range to optimize noise performance. The "break-before-make" time may need to be increased if slew control is implemented, especially for slower transition rates. Adjustment can be done by increasing the value of RT (CT can be reduced to maintain the same frequency of operation), to ensure that the bridge MOSFETs receive nonoverlapping drive. Power MOSFET Selection Four external MOSFETs must be selected for use with the LTC1923; a pair of N-channel MOSFETs for the bottom of the bridge and a pair of P-channel MOSFETs for the top diagonals of the bridge. The MOSFETs should be selected for their RDS(ON), gate charge and maximum VDS, VGS ratings. A maximum VDS rating of 20V is more than sufficient for 5V and 12V bridge applications, but as mentioned in the High Voltage Application section, a 12V maximum VGS rating is insufficient and higher voltage MOSFETs must be selected. There is a trade-off between RDS(ON) and gate charge. The RDS(ON) affects the conduction losses (ITEC2 * RDS(ON)), while gate charge is a dominant contributor to switching losses. A higher RDS(ON) MOSFET typically has a smaller gate capacitance and thus requires less current to charge the gate for the same BVDSS. For 1A TEC applications, the Si9801DY or Si9928DY complimentary N- and P-channel MOSFETs provide a 22 U good trade-off between switching and conduction losses. Above this TEC current level the MOSFETs selected should have lower RDS(ON) to maintain the high end efficiency. Efficiency Considerations Unlike typical voltage regulators, where the output voltage is fixed, independent of load current, the output voltage of this regulator changes with load current. This is because the TEC appears resistive and the current through the TEC sets the voltage. The output power of the regulator is defined as: POUT = ITEC2 * RTEC The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. Often it is useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most significant improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. For this application, the main efficiency concern is typically at the high end of output power. A higher power loss translates into a greater system temperature rise, resulting in the need for heat sinking, increasing both the system size and cost. There are three main sources which usually account for most of the losses in the application shown on the front page of the data sheet: Input supply current, MOSFET switching losses and I2R losses. 1) The input supply current is comprised of the quiescent current draw from the LTC1658, LTC2053, LTC1923 and any additional circuitry added. The total maximum supply current for these devices is on the order of 5mA, which gives a total power dissipation of 25mW. This power loss is independent of TEC current. 2) The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a gate is switched from low to high to low again, a packet of charge dQ moves from VDD to ground. The gate charging current, IGATECHG = 2 * f * (QP + QN), where QP and QN are 1923f W UU LTC1923 APPLICATIO S I FOR ATIO the total gate charges of the NMOS and PMOS on one side of the bridge, and f is the oscillator frequency. The factor of 2 arises from there being two sets of MOSFETs that make up the full bridge. Note that increasing the switching frequency will increase the dynamic current and therefore power dissipation by the same factor. This power loss is independent of TEC current. Example: QN = 10nC max, QP = 15nC max, f = 225kHz, VDD = 5V Power loss = 2 * f * (QP + QN) * VDD = 56mW 3) The DC resistances of the external bridge MOSFETs, filter inductors and sense resistor are typically the dominant loss mechanism at the high end TEC current. The conduction path of the current includes one NMOS, one PMOS, two inductors and the sense resistor so the DC resistances associated with the components dissipate power. Example: RDS(ON)NMOS at 5V = 0.055 max RDS(ON)PMOS at 5V = 0.08 max RS = 0.1 RL = 0.1, ITEC = 1A RTEC = 2.5 250 10k 250 1F 10k NTC REF LTC1658 VOUT Figure 14. Low Input Supply Voltage Circuit 1923f U Total series resistance = 0.055 + 0.08 + 2 * 0.1 + 0.1 = 0.435 Power Loss = (1A)2 * 0.435 = 0.435W Output Power = (1A)2 * 2.5 = 2.5W This represents a 17% efficiency loss due to conduction losses. The other two power loss mechanisms comprise a little more than a 3% efficiency loss at this output power level. This may sound alarming if electrical efficiency is the primary concern and can be easily improved by choosing lower RDS(ON) MOSFETs, lower series resistance inductors and a smaller valued sense resistor. If temperature rise is the primary concern, this power dissipation may be acceptable. At higher current levels, this example does illustrate that lower resistance components should be selected. Low Voltage Requirements All components shown on the front page of this data sheet will operate with a 2.7V input supply. Minor modifications are required to guarantee correct operation. The voltage on the REF input of the LTC2053 should be at least 1V below VDD. Figure 14 shows how to implement this. By dividing down the 2.5V reference with 500 of impedance, feeding this to the REF input of the LTC2053 and the integrating resistor of the LTC1923 error amplifier, any common mode issues will be avoided. + - REF CNTRL VREF EAOUT A = 10 100k 10M 4.7F LTC1923GN FB VSET VTHRM 1923 F14 W UU LTC2053 1F VDD VDD 2.7V TO 3.3V 23 LTC1923 APPLICATIO S I FOR ATIO Higher Voltage Applications A bank of TECs can be wired in series to minimize board real estate utilized by the application. A higher voltage supply may be required depending upon how many TECs are placed in series and what their maximum voltage drop is. In other applications, only one high current supply may be available, with the output voltage of this supply being greater than the LTC1923's absolute maximum voltage rating. The absolute maximum input voltage for the LTC1923 is 6V. Since the current drawn by the LTC1923 is small, it can be powered from a low current, 5V (or less) supply. A 12V application for driving the full bridge is shown in Figure 15. Two LTC1693-1 high speed dual MOSFET drivers are used to step up the lower voltage produced by the LTC1923 drivers to the higher voltage levels required to drive the full bridge. The LTC1693 requires proper bypassing and grounding due to its high switching speed and large AC currents. Mount the low ESR bypass capacitors as close to the pins as possible, shortening the leads as much as possible to reduce inductance. Refer to the LTC1693 data sheet for more information. Since the LTC1693-1 low-to-high and highto-low propagation delays are almost identical (typically 35ns), there is minimal skew introduced by the addition of these drivers. Sufficient dead time (typically 50ns) between one leg of the bridge shutting off and the other turning on, as set up by the LTC1923, will be maintained. If this dead time is insufficient, the resistor tied to the R T pin can be increased to increase this time. Care must be taken to ensure that the external MOSFETs are properly selected based on the maximum drain-source voltage, VDS, gate-source voltage, VGS, and RDS(ON). Many MOSFETs that have an absolute maximum VDS of 20V have a maximum VGS of only 12V, which is insufficient for 12V applications. Even the 14V maximum VGS rating of the Si9801DY may not provide adequate margin for a 12V bridge supply voltage. Refer to Efficiency Considerations for more discussion about selecting a MOSFET with RDS(ON). 24 U Two pairs of resistors, RT1 and RT2, must be added to ensure that the absolute maximum input voltage is not exceeded on the TEC + and TEC - inputs. The maximum voltage on TEC + and TEC - must be less than the VDD input supply to the LTC1923 which, for this example, is 5V. The following equation will guarantee this: W UU VBRIDGE < VDD RT 1 RT 1 + 1+ RT 2 100k where VBRIDGE is the supply voltage to the external bridge circuitry and VDD is the input supply to the LTC1923. These additional level shifting resistors affect some parameters in the data sheet. The direction comparator thresholds are increased to: (1 + RT1/RT2 + RT1/100k) * 50mV and (1 + RT1/RT2 + RT1/100k) * - 50mV The output voltage on the VTEC pin represents the voltage across the TEC (VTECOOLER) reduced by a factor of (1 + RT1/RT2 + RT1/100k) or: VVTEC = VTECOOLER/(1 + RT1/RT2 + RT1/100k) The term containing 100k is the loading error introduced by the input impedance of the differential amplifier. Typically this value will be 100k, but can vary due to normal process tolerances and temperature (up to 30%). Due to this variability, it may be desirable to minimize the loading effect to try to keep a tight tolerance on the TEC clamp voltage. Although it will increase quiescent current draw, this can be accomplished by making the value of RT1 as small as possible. As a result of this level shifting, the TEC voltage necessary to activate the clamp is raised. The voltage across the TEC where the voltage clamp activates will be: VTECOOLER = (1 + RT1/RT2 + RT1/100k) * 2.5V One drawback with using the LTC1693 MOSFET drivers is the inability to adjust the slew rate of the output drivers to reduce system noise. 1923f LTC1923 APPLICATIO S I FOR ATIO PLLLPF RSLEW SDSYNCB CNTRL EAOUT FB RT CT LTC1693-1 VREF PDRVB NDRVB VDD 5V 1F IN1 VCC1 10F 4.7F TEC 0.1F 4.7F LTC1693-1 IN1 VCC1 3 1 RS 2 4 47F GND1 OUT1 IN2 VCC2 GND2 OUT2 0.1F AGND PGND LTC1923 SS NDRVA ILIM VSET FAULT VTHRM H/C VTEC PDRVA CS + CS - ITEC TEC + TEC - GND1 OUT1 IN2 VCC2 GND2 OUT2 Figure 15. Higher Voltage Applications with the LTC1923 U 12V RT1 RT1 RT2 RT2 1923 F15 W UU 1923f 25 LTC1923 REF CLK U2 7 2 LTC1658IMS8 DIN VOUT 14 BIT 3 CS/LD DOUT GND 4 CNTRL PDRVB NDRVB 23 L1 10H TEC C7 0.1F C16 22F 6.3V C15 22F 6.3V 22 21 20 19 18 17 16 15 1923 TA02 R10 10M 1% EAOUT VDD C14 1F TEC + FB VDD U1 LTC1923EGN PGND NDRVA PDRVA CS + CS - ITEC TEC + TEC - R15 0.1 0.5W 1% AGND SS ILIM VSET FAULT VTHRM H/C VTEC Q1 Si9801DY TEC - R13 100k 1% 7 C18 1F 8 9 10 11 4 R14 1k 1% VSET C19 1F 5 C11 0.1F SM FILM NTC + RT1 THERMISTOR 10k NTC NTC - VSET VDD 12 R20 100k 13 14 HEAT VDD COOL R25 200 VDD R26 100k Q6 2N7002 Q5 2N7002 OPTIONAL FOR VISUAL HEATING/COOLING INDICATION VDD R27 200 D5 LED (GRN) R23 100k D4 LED (ORN) VDD FAULT VDD VDD R19 200 D3 LED (RED) R20 100k Q3 2N7002 Q4 2N7002 OPTIONAL FOR VISUAL FAULT INDICATION Laser Temperature Control Loop Achieving Set Point Stability of 0.01C + CS/LD 5 6 R9 9.09K 1% C13 4.7F 20V 5 24 C10 0.1F SM FILM L2 10H C17 22F 6.3V Q2 Si9801DY C2, C3, C4, C7, C8: AVX 0603YC104KAT1A (X7R, 16V) C5: AVX 06035A331KAT1A (NPO, 50V) C6, C14, C18, C19: AVX 06036D105KAT2A (X5R, 6.3V) C9: TAIYO YUDEN JMK316BJ106ML-T (X7R, 6.3V) C10, C11: PANASONIC ECP-U1C104MA5 (SM FILM, 16V) C13: AVX TAJA475M020R (TANTALUM, 20V) C15, C16, C17: TAIYO YUDEN JMK325BJ226MM-T (X7R, 6.3V) D3 (OPTIONAL): PANASONIC LN1251-C-TR (RED) D4 (OPTIONAL): PANASONIC LN1851-C-TR (ORANGE) D5 (OPTIONAL): PANASONIC LN1351-C-TR (GREEN) L1, L2: SUMIDA CDRH6D28-100NC Q1, Q2: SILICONIX Si9801DY Q3, Q4, Q5, Q6 (OPTIONAL): 2N7002 R3: KOA RN73T2AT1002B O.1% R15: KOA SR73H2ER100F ALL RESISTORS 5% TOLERANCE UNLESS NOTED R10, R13, C13 MAY NEED TO BE CHANGED TO ACHIEVE DESIRED LOOP RESONSE U 26 VDD 0.1F 10k 1 PLLLPF C5 330pF 27 VSET C6 1F C9 10F 6.3V 26 25 VDD VDD RSLEW CT VREF SDSYNC RT 28 R1 10k C8 0.1F R4 82k 2 8 3 3 C4 0.1F VDD R3 VSET 10k 0.1% C2 0.1F C3 0.1F 8 6 R7 10k 1% CLK 2 TYPICAL APPLICATIO 1 VCC + - 6 4 U3 1 LTC2053IMS8 7 VDD DIN 1923f LTC1923 PACKAGE DESCRIPTIO 0.015 0.004 x 45 (0.38 0.10) 0.0075 - 0.0098 (0.191 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) 0.386 - 0.393* (9.804 - 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 0.033 (0.838) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.053 - 0.069 (1.351 - 1.748) 23 4 56 7 8 9 10 11 12 13 14 0.004 - 0.009 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC GN28 (SSOP) 1098 1923f 27 LTC1923 PACKAGE DESCRIPTIO 5.35 0.05 4.20 0.05 3.45 0.05 (4 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (4 SIDES) 0.75 0.05 0.00 - 0.05 PIN 1 TOP MARK NOTE: 1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED RELATED PARTS PART NUMBER LTC1658 LTC1693-1 LTC2053 DESCRIPTION 14-Bit Rail-to-Rail Micropower DAC High Speed Dual N-Channel MOSFET Driver Zero Drift Instrumentation Amp COMMENTS 3V or 5V Single Supply Operation, ICC = 270A, 8-Lead MSOP Package 1.5A Peak Output Current, 1G Electrical Isolation, SO-8 Package Max Gain Error 0.01%, Input Offset Drift of 50nV/C, Input Offset Voltage of 10V 1923f LT/TP 0502 2K * PRINTED IN USA 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U UH Package 32-Lead Plastic QFN (5mm x 5mm) (Reference LTC DWG # 05-08-1693) 0.57 0.05 PACKAGE OUTLINE 0.23 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 31 32 0.40 0.10 1 2 3.45 0.10 (4-SIDES) (UH) QFN 0102 0.200 REF 0.23 0.05 0.50 BSC www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2001 |
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